Skip to content

Commit 281a1a0

Browse files
thejpsterthejpster
committed
Merge branch 'release/v0.5.1'
2 parents 4edc215 + 986ea9f commit 281a1a0

File tree

12 files changed

+559
-263
lines changed

12 files changed

+559
-263
lines changed

‎.github/workflows/build_and_release.yml‎

Lines changed: 5 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,19 @@
11
on: [push, pull_request]
22
name: Build (and Release)
33

4+
env:
5+
CARGO_TERM_COLOR: always
6+
47
jobs:
58
build:
69
name: Build (and Release)
710
runs-on: ubuntu-latest
811
steps:
912
- name: Checkout
10-
uses: actions/checkout@v1
13+
uses: actions/checkout@v3
1114
with:
1215
submodules: true
16+
fetch-depth: 0
1317

1418
- name: Add targets
1519
run: |
@@ -28,24 +32,6 @@ jobs:
2832
- name: Build neotron-bmc-nucleo
2933
run: cd neotron-bmc-nucleo && DEFMT_LOG=info cargo build --release --verbose --target=thumbv7em-none-eabihf
3034

31-
- name: Get Branch Name
32-
if: github.event_name == 'push' && startswith(github.ref, 'refs/tags/')
33-
id: branch_name
34-
run: |
35-
echo ::set-output name=SOURCE_TAG::${GITHUB_REF#refs/tags/}
36-
37-
- name: Create Release
38-
if: github.event_name == 'push' && startswith(github.ref, 'refs/tags/')
39-
id: create_release
40-
uses: actions/create-release@v1
41-
env:
42-
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
43-
with:
44-
tag_name: ${{ github.ref }}
45-
release_name: Release ${{ steps.branch_name.outputs.SOURCE_TAG }}
46-
draft: false
47-
prerelease: false
48-
4935
- name: Upload files to Release
5036
if: github.event_name == 'push' && startswith(github.ref, 'refs/tags/')
5137
uses: softprops/action-gh-release@v1

‎CHANGELOG.md‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,12 @@
44

55
* None
66

7+
## v0.5.1
8+
9+
* Adds a PC speaker driver using TIM14
10+
* Plays a beep on startup
11+
* Lets the host play beeps using the SPI interface
12+
713
## v0.5.0
814

915
* Generates Host Interrupts

‎README.md‎

Lines changed: 5 additions & 221 deletions
Original file line numberDiff line numberDiff line change
@@ -43,233 +43,17 @@ See the [board-specific README](./neotron-bmc-nucleo/README.md).
4343

4444
It's currently quite out of date compared to the Neotron Pico version.
4545

46-
## SPI Communications Protocol
46+
## BMC Registers
4747

48-
The SPI interface runs in SPI mode 0 (clock line idles low, data sampled on
49-
rising edge) at 1 MHz (higher speeds TBD). It uses frames made up of 8-bit
50-
words.
51-
52-
To communicate with the NBMC, the Host Processor must first take the Chip Select
53-
line (`SPI1_nCS`) low, then send a Header. SPI is a full-duplex system, but in
54-
this system only one side is actually transferring useful data at any time, so
55-
whilst the Header is being sent the Host will receive Padding Bytes of `0xFF` in
56-
return (which can be discarded).
57-
58-
The NBMC exposes a number of registers - some can be read, some can be written
59-
to, some are cleared when written to.
60-
61-
See [neotron-bmc-protocol's README](./neotron-bmc-protocol/README.md) for more
62-
details of how the registers are accessed. The registers themselves are defined
63-
below.
64-
65-
## System Registers
66-
67-
| Address | Name | Type | Contains | Length |
68-
| :-----: | ------------------------------------- | :---: | -------------------------------------------------------- | :------: |
69-
| 0x00 | Protocol Version | RO | The NBMC protocol version, [1, 0, 0] | 3 |
70-
| 0x01 | Firmware Version | RO | The NBMC firmware version, as a null-padded UTF-8 string | 32 |
71-
| 0x10 | Interrupt Status | R/W1C | Which interrupts are currently active, as a bitmask. | 2 |
72-
| 0x11 | Interrupt Control | R/W | Which interrupts are currently enabled, as a bitmask. | 2 |
73-
| 0x20 | Button Status | RO | The current state of the buttons | 1 |
74-
| 0x21 | System Temperature | RO | Temperature in °C, as an `i8` | 1 |
75-
| 0x22 | System Voltage (Standby 3.3V rail) | RO | Voltage in Volts/32, as a `u8` | 1 |
76-
| 0x23 | System Voltage (Main 3.3V rail) | RO | Voltage in Volts/32, as a `u8` | 1 |
77-
| 0x24 | System Voltage (5.0V rail) | RO | Voltage in Volts/32, as a `u8` | 1 |
78-
| 0x25 | Power Control | R/W | Enable/disable the power supply | 1 |
79-
| 0x30 | UART Receive/Transmit Buffer | FIFO | Data received/to be sent over the UART | up to 64 |
80-
| 0x31 | UART FIFO Control | R/W | Settings for the UART FIFO | 1 |
81-
| 0x32 | UART Control | R/W | Settings for the UART | 1 |
82-
| 0x33 | UART Status | R/W1C | The current state of the UART | 1 |
83-
| 0x34 | UART Baud Rate | R/W | The UART baud rate in bps, as a `u32le` | 4 |
84-
| 0x40 | PS/2 Keyboard Receive/Transmit Buffer | FIFO | Data received/to be sent over the PS/2 keyboard port | up to 16 |
85-
| 0x41 | PS/2 Keyboard Control | R/W | Settings for the PS/2 Keyboard port | 1 |
86-
| 0x42 | PS/2 Keyboard Status | R/W1C | Current state of the PS/2 Keyboard port | 1 |
87-
| 0x50 | PS/2 Mouse Receive/Transmit Buffer | FIFO | Data received/to be sent over the PS/2 Mouse port | up to 16 |
88-
| 0x51 | PS/2 Mouse Control | R/W | Settings for the PS/2 Mouse port | 1 |
89-
| 0x52 | PS/2 Mouse Status | R/W1C | Current state of the PS/2 Mouse port | 1 |
90-
| 0x60 | I²C Receive/Transmit Buffer | FIFO | Data received/to be sent over the I²C Bus | up to 16 |
91-
| 0x61 | I²C FIFO Control | R/W | Settings for the I²C FIFO | 1 |
92-
| 0x62 | I²C Control | R/W | Settings for the I²C Bus | 1 |
93-
| 0x63 | I²C Status | R/W1C | Current state of the I²C Bus | 1 |
94-
| 0x64 | I²C Baud Rate | R/W | The I²C clock rate in Hz, as a `u32le` | 4 |
95-
96-
The register types are:
97-
98-
* `RO` - read only register, where writes will return an error
99-
* `R/W` - read/write register
100-
* `R/W1C` - reads as usual, but when writing a 1 bit clears that bit position and a 0 bit is ignored
101-
* `FIFO` - a first-in, first-out buffer
102-
103-
### Address 0x01 - Protocol Version
104-
105-
This read-only register returns the protocol version supported. The protocol
106-
version includes the set of registers, and the meaning of the fields within
107-
those registers. A *Host* should first verify that the *NBMC* it is talking to
108-
is semantically compatible before reading any other registers.
109-
110-
The three bytes are `major`, `minor` and `patch`. This document corresponds to
111-
`[1, 0, 0]` (or *v1.0.0*).
112-
113-
### Address 0x01 - Firmware Version
114-
115-
This read-only register returns the firmware version of the NBMC, as a UTF-8
116-
string. The register length is always 64 bytes, and the string is null-padded.
117-
We also guarantee that the firmware version will always be less than or equal to
118-
63 bytes, so you can also treat this string as null-terminated.
119-
120-
An official release will have a version string of the form `tags/v1.2.3`. An
121-
unofficial release might be `heads/develop-dirty`. It is not recommended that
122-
you rely on these formats or attempt to parse the version string. It is however
123-
useful if you can quote this string when reporting issues with the firmware.
124-
125-
### Address 0x02 - Interrupt Status
126-
127-
This eight bit register indicates which Interrupts are currently 'active'. An
128-
Interrupt will remain 'active' until a word is written to this register with a 1
129-
bit in the relevant position.
130-
131-
| Bit | Interrupt |
132-
| --- | -------------------------- |
133-
| 7 | Voltage Alarm |
134-
| 6 | Button State Change |
135-
| 5 | UART TX Empty |
136-
| 4 | UART RX Not Empty |
137-
| 3 | I²C TX Empty |
138-
| 2 | I²C RX Not Empty |
139-
| 1 | PS/2 Mouse RX Not Empty |
140-
| 0 | PS/2 Keyboard RX Not Empty |
141-
142-
### Address 0x03 - Interrupt Control
143-
144-
This eight bit register indicates which Interrupts are currently 'enabled'. The
145-
IRQ_nHOST signal is a level interrupt and it will be active (LOW) whenever the
146-
value in the Interrupt Control register ANDed with the Interrupt Status register
147-
is non-zero.
148-
149-
The bits have the same ordering as the Interrupt Status register.
150-
151-
### Address 0x04 - Button Status
152-
153-
This eight-bit register indicates the state of the power button.
154-
155-
Note that if the power button is held down for three seconds, the system will
156-
power-off instantly, regardless of what the host does.
157-
158-
Note also that is it not possible to sample the reset button - pressing the
159-
reset button will instantly assert the system reset line, rebooting the Host.
160-
161-
| Bits | Meaning |
162-
| ---- | ------------------------------------- |
163-
| 7-1 | Reserved for future use |
164-
| 0 | Power Button: 0 = normal, 1 = pressed |
165-
166-
### Address 0x04 - System Temperature
167-
168-
This eight-bit register provides the current system temperature in °C, as
169-
measured on the STM32's internal temperature sensor. It is updated around once a
170-
second.
171-
172-
### Address 0x05 - System Voltage (Standby 3.3V rail)
173-
174-
This eight-bit register provides the current 3.3V rail voltage in units of 1/32
175-
of a Volt. It is updated around once a second. A value of 105 (3.28V) to 106
176-
(3.31V) is nominal. An interrupt is raised when the value exceeds 3.63V (116) or
177-
is lower than 2.97V (95).
178-
179-
### Address 0x06 - System Voltage (Main 3.3V rail)
180-
181-
This eight-bit register provides the current 3.3V rail voltage in units of 1/32
182-
of a Volt. It is updated around once a second. A value of 105 (3.28V) to 106
183-
(3.31V) is nominal. An interrupt is raised when the value exceeds 3.63V (116) or
184-
is lower than 2.97V (95).
185-
186-
### Address 0x07 - System Voltage (5.0V rail)
187-
188-
This eight-bit register provides the current 3.3V rail voltage in units of 1/32
189-
of a Volt. It is updated around once a second. A value of 160 (5.00V) is
190-
nominal. An interrupt is raised when the value exceeds 5.5V (176) or is lower
191-
than 4.5V (144).
192-
193-
### Address 0x08 - Power Control
194-
195-
This eight-bit register controls the main DC/DC power supply unit. The Host
196-
should disable the DC/DC supply (by writing zero here) if it wishes to power
197-
down.
198-
199-
| Bits | Meaning |
200-
| ---- | ------------------------------ |
201-
| 7-1 | Reserved for future use |
202-
| 0 | DC/DC control: 0 = off, 1 = on |
203-
204-
### Address 0x10 - UART Receive/Transmit Buffer
205-
206-
TODO
207-
208-
### Address 0x11 - UART FIFO Control
209-
210-
TODO
211-
212-
### Address 0x12 - UART Control
213-
214-
TODO
215-
216-
### Address 0x13 - UART Status
217-
218-
TODO
219-
220-
### Address 0x14 - UART Baud Rate
221-
222-
TODO
223-
224-
### Address 0x20 - PS/2 Keyboard Receive/Transmit Buffer
225-
226-
TODO
227-
228-
### Address 0x21 - PS/2 Keyboard Control
229-
230-
TODO
231-
232-
### Address 0x22 - PS/2 Keyboard Status
233-
234-
TODO
235-
236-
### Address 0x30 - PS/2 Mouse Receive/Transmit Buffer
237-
238-
TODO
239-
240-
### Address 0x31 - PS/2 Mouse Control
241-
242-
TODO
243-
244-
### Address 0x32 - PS/2 Mouse Status
245-
246-
TODO
247-
248-
### Address 0x40 - I²C Receive/Transmit Buffer
249-
250-
TODO
251-
252-
### Address 0x41 - I²C FIFO Control
253-
254-
TODO
255-
256-
### Address 0x42 - I²C Control
257-
258-
TODO
259-
260-
### Address 0x43 - I²C Status
261-
262-
TODO
263-
264-
### Address 0x44 - I²C Baud Rate
265-
266-
TODO
48+
See the [neotron-bmc-protocol](./neotron-bmc-protocol/README.md) and
49+
[neotron-bmc-commands](./neotron-bmc-commands/README.md) for more details on how
50+
the BMC registers are accessed and modified.
26751

26852
## Build Requirements
26953

27054
Build requirements are available for
27155
[Neotron-BMC-pico](neotron-bmc-pico/README.md) and
272-
[Neotron-BMC-nucleo](neotron-bmc-nucleo/README.md).
56+
[Neotron-BMC-nucleo](neotron-bmc-nucleo/README.md).
27357

27458
## Licence
27559

0 commit comments

Comments
 (0)