Popular repositories Loading

1. VLSI VLSI Public

   Low-power BCD adder in 45nm CMOS achieving 68% power reduction | M.Tech VLSI Thesis project

   Verilog

2. edgeconv-pd edgeconv-pd Public

   Verilog

3. multi_clock_cdc_asic multi_clock_cdc_asic Public

   Complete RTL TO GDS II ASIC DESIGN FLOW [ MULTI CLOCK CDC SYSTEM SKYWATER NM]

   Verilog