[CK] Add new fwd conv fp16/bf16 instances optimized for unit group size. #3670
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vpietila-amd
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vidyasagar-amd
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bartekxk
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Jan 28, 2026
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Pull request overview
This PR adds new FP16 and BF16 convolution instances optimized for unit group size (G=1) to improve performance. The new instances leverage the compute-optimized block GEMM pipeline and demonstrate significant performance improvements (up to 14% TFLOP increase).
Changes:
- Added two new BF16 instances optimized for G=1 with different block configurations (256x256x256 and 512x128x32)
- Added two new FP16 instances optimized for G=1 with matching block configurations
- Modified line endings to add commas for existing instances to accommodate new entries
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| DeviceGroupedConvFwdMultipleABD_Xdl_CShuffle_V3<NDimSpatial,ALayout,BLayout, DsLayout,ELayout, F16, F16, F32, F16, DsDataTypes, F16, PassThrough, PassThrough, OutElementOp, ConvSpec, GemmMNKPadding, 256, 128, 128, 64, 8, 8, 32, 32, 2, 2, S<8, 32, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 0, S<8, 32, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 0, 1, 1, S<1, 32, 1, 8>, 8, BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v4> | ||
| // clang-format on | ||
| DeviceGroupedConvFwdMultipleABD_Xdl_CShuffle_V3<NDimSpatial,ALayout,BLayout, DsLayout,ELayout, F16, F16, F32, F16, DsDataTypes, F16, PassThrough, PassThrough, OutElementOp, ConvSpec, GemmMNKPadding, 256, 128, 128, 64, 8, 8, 32, 32, 2, 2, S<8, 32, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 0, S<8, 32, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 0, 1, 1, S<1, 32, 1, 8>, 8, BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v4>, | ||
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Empty line contains trailing whitespace. Remove the trailing whitespace to maintain code cleanliness.
Suggested change
vpietila-amd
commented
Jan 29, 2026
...tensor_operation_instance/gpu/grouped_conv_fwd/device_grouped_conv_fwd_xdl_comp_instance.hpp
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January 29, 2026 10:19
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Proposed changes
Added new FP16/BF16 instances that are optimized for group size = 1. The new instance use the compute optimized block GEMM pipeline.