[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] update hygon qos to new version #1471

opsiff · 2026-02-02T02:40:34Z

Tianxiang Peng (1):
x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper

Wentao Guan (1):
Revert "x86/resctrl: Add Hygon QoS support"

Xiaochen Shen (2):
x86/resctrl: Add missing resctrl initialization for Hygon
x86/resctrl: Fix memory bandwidth counter width for Hygon

arch/x86/kernel/cpu/hygon.c | 1 +
arch/x86/kernel/cpu/resctrl/core.c | 17 +++++++++++++----
arch/x86/kernel/cpu/resctrl/internal.h | 3 +++
3 files changed, 17 insertions(+), 4 deletions(-)

Summary by Sourcery

Update Hygon resctrl QoS support and detection to align with upstream behavior.

Bug Fixes:

Correctly initialize Hygon resctrl support during BSP CPU setup.
Fix Hygon memory bandwidth monitoring counter width by using a Hygon-specific width offset instead of sharing the AMD value.

Enhancements:

Refine resctrl CPU detection logic to select vendor-specific MBM counter width offsets for AMD and Hygon, leaving others unchanged.

This reverts commit d242f92.

commit d8df126 upstream. Since 923f3a2 ("x86/resctrl: Query LLC monitoring properties once during boot") resctrl_cpu_detect() has been moved from common CPU initialization code to the vendor-specific BSP init helper, while Hygon didn't put that call in their code. This triggers a division by zero fault during early booting stage on our machines with X86_FEATURE_CQM* supported, where get_rdt_mon_resources() tries to calculate mon_l3_config with uninitialized boot_cpu_data.x86_cache_occ_scale. Add the missing resctrl_cpu_detect() in the Hygon BSP init helper. [ bp: Massage commit message. ] Fixes: 923f3a2 ("x86/resctrl: Query LLC monitoring properties once during boot") Signed-off-by: Tianxiang Peng <txpeng@tencent.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Hui Li <caelli@tencent.com> Cc: <stable@kernel.org> Link: https://lore.kernel.org/20250623093153.3016937-1-txpeng@tencent.com Signed-off-by: Tianxiang Peng <txpeng@tencent.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 7207923d8453ebfb35667c1736169f2dd796772e) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

commit 6ee98aabdc700b5705e4f1833e2edc82a826b53b upstream. Hygon CPUs supporting Platform QoS features currently undergo partial resctrl initialization through resctrl_cpu_detect() in the Hygon BSP init helper and AMD/Hygon common initialization code. However, several critical data structures remain uninitialized for Hygon CPUs in the following paths: - get_mem_config()-> __rdt_get_mem_config_amd(): rdt_resource::membw,alloc_capable hw_res::num_closid - rdt_init_res_defs()->rdt_init_res_defs_amd(): rdt_resource::cache hw_res::msr_base,msr_update Add the missing AMD/Hygon common initialization to ensure proper Platform QoS functionality on Hygon CPUs. Fixes: d8df126 ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper") Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251209062650.1536952-2-shenxiaochen@open-hieco.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit a78dca14fb2b054d7b8b46bda1ea552bd1a88ffe) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

commit 7517e899e1b87b4c22a92c7e40d8733c48e4ec3c upstream. The memory bandwidth calculation relies on reading the hardware counter and measuring the delta between samples. To ensure accurate measurement, the software reads the counter frequently enough to prevent it from rolling over twice between reads. The default Memory Bandwidth Monitoring (MBM) counter width is 24 bits. Hygon CPUs provide a 32-bit width counter, but they do not support the MBM capability CPUID leaf (0xF.[ECX=1]:EAX) to report the width offset (from 24 bits). Consequently, the kernel falls back to the 24-bit default counter width, which causes incorrect overflow handling on Hygon CPUs. Fix this by explicitly setting the counter width offset to 8 bits (resulting in a 32-bit total counter width) for Hygon CPUs. Fixes: d8df126 ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper") Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251209062650.1536952-3-shenxiaochen@open-hieco.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit b73f2834e1bc6daeb67ef43404149073e7dccadb) Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

sourcery-ai · 2026-02-02T02:40:40Z

Reviewer's guide (collapsed on small PRs)

Reviewer's Guide

Updates Hygon resctrl (QoS) support by ensuring Hygon CPUs run the common resctrl detection path, defining a Hygon-specific MBM counter width offset, and switching cache MBM width handling to a vendor-specific switch that uses the new Hygon value instead of the previous AMD/Hygon sharing, effectively reverting the earlier generic Hygon QoS addition and replacing it with the updated implementation.

Sequence diagram for Hygon CPU init calling common resctrl detection

sequenceDiagram
    actor CPUStartup
    participant bsp_init_hygon
    participant resctrl_cpu_detect

    CPUStartup->>bsp_init_hygon: initialize Hygon BSP(cpuinfo_x86 c)
    bsp_init_hygon->>bsp_init_hygon: Hygon specific setup
    bsp_init_hygon->>resctrl_cpu_detect: resctrl_cpu_detect(c)

    resctrl_cpu_detect->>resctrl_cpu_detect: Read CPUID for resctrl
    resctrl_cpu_detect->>resctrl_cpu_detect: Set c.x86_cache_occ_scale, c.x86_cache_mbm_width_offset
    alt c.x86_cache_mbm_width_offset == 0
        alt c.x86_vendor == X86_VENDOR_AMD
            resctrl_cpu_detect->>resctrl_cpu_detect: c.x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD
        else c.x86_vendor == X86_VENDOR_HYGON
            resctrl_cpu_detect->>resctrl_cpu_detect: c.x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_HYGON
        else other vendor
            resctrl_cpu_detect->>resctrl_cpu_detect: leave c.x86_cache_mbm_width_offset = 0
        end
    else nonzero offset from CPUID
        resctrl_cpu_detect->>resctrl_cpu_detect: keep existing offset
    end

    resctrl_cpu_detect-->>bsp_init_hygon: return
    bsp_init_hygon-->>CPUStartup: BSP init complete

Class diagram for updated resctrl and Hygon CPU structures

classDiagram
    class cpuinfo_x86 {
        int x86_vendor
        unsigned int x86_cache_occ_scale
        unsigned int x86_cache_mbm_width_offset
    }

    class resctrl_core_c {
        +void resctrl_cpu_detect(cpuinfo_x86 *c)
        MBM_CNTR_WIDTH_OFFSET_AMD = 20
        MBM_CNTR_WIDTH_OFFSET_HYGON = 8
    }

    class hygon_c {
        +void bsp_init_hygon(cpuinfo_x86 *c)
    }

    cpuinfo_x86 <.. resctrl_core_c : uses
    cpuinfo_x86 <.. hygon_c : uses
    resctrl_core_c <.. hygon_c : calls

    class Vendors {
        X86_VENDOR_AMD
        X86_VENDOR_HYGON
        other_vendors
    }

    Vendors <.. cpuinfo_x86 : x86_vendor

    class MBMOffsets {
        MBM_CNTR_WIDTH_BASE
        MBM_CNTR_WIDTH_OFFSET_AMD
        MBM_CNTR_WIDTH_OFFSET_HYGON
    }

    MBMOffsets <.. resctrl_core_c : defines counter width behavior

File-Level Changes

Change	Details	Files
Route Hygon BSP initialization through the common resctrl CPU detection helper.	Call resctrl_cpu_detect() at the end of bsp_init_hygon() so that Hygon CPUs get standard resctrl detection and setup during boot	`arch/x86/kernel/cpu/hygon.c`
Introduce a Hygon-specific MBM counter width offset constant for resctrl.	Define MBM_CNTR_WIDTH_OFFSET_HYGON as 8, documenting it as the Hygon MBM counter width offset from MBM_CNTR_WIDTH_BASE	`arch/x86/kernel/cpu/resctrl/internal.h`
Adjust resctrl MBM width detection to use vendor-specific offsets, including the new Hygon offset.	Replace the AMD/Hygon combined conditional with a switch over x86_vendor that sets AMD MBM width offset to MBM_CNTR_WIDTH_OFFSET_AMD and Hygon to MBM_CNTR_WIDTH_OFFSET_HYGON when no CPUID-provided width is present Preserve behavior for other vendors by leaving x86_cache_mbm_width_offset at 0 when not handled explicitly	`arch/x86/kernel/cpu/resctrl/core.c`

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deepin-ci-robot · 2026-02-02T02:40:43Z

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Avenger-285714 · 2026-02-02T11:29:32Z

arch/x86/kernel/cpu/hygon.c

 			x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
 		}
 	}
+


Is the purpose here to align with the upstream code version?

Right, you can see ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper") here,https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/x86/kernel/cpu/hygon.c?h=v6.6.122&id=7207923d8453ebfb35667c1736169f2dd796772e

Copilot

Pull request overview

This PR updates Hygon QoS (Quality of Service) support to align with upstream changes. The key change is separating Hygon's Memory Bandwidth Monitoring (MBM) counter width offset from AMD's, since they have different hardware implementations. Hygon processors use an offset of 8 while AMD uses 20.

Changes:

Define a Hygon-specific MBM counter width offset constant (value: 8)
Refactor vendor-specific MBM counter width detection from if-statement to switch-statement for better maintainability
Add blank line in Hygon BSP initialization for consistency with AMD implementation

Reviewed changes

Copilot reviewed 3 out of 3 changed files in this pull request and generated no comments.

File	Description
arch/x86/kernel/cpu/resctrl/internal.h	Adds MBM_CNTR_WIDTH_OFFSET_HYGON constant definition
arch/x86/kernel/cpu/resctrl/core.c	Refactors MBM counter width offset detection to use switch-statement, separating Hygon and AMD handling
arch/x86/kernel/cpu/hygon.c	Adds blank line before resctrl_cpu_detect() call for code style consistency

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opsiff and others added 4 commits February 2, 2026 10:29

Revert "x86/resctrl: Add Hygon QoS support"

6b3a41f

This reverts commit d242f92.

deepin-ci-robot requested review from Wenlp and chenchongbiao February 2, 2026 02:40

sourcery-ai bot reviewed Feb 2, 2026

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Avenger-285714 requested review from Avenger-285714 and Copilot February 2, 2026 11:28

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[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] update hygon qos to new version #1471

[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] update hygon qos to new version #1471

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Reviewer's Guide

Sequence diagram for Hygon CPU init calling common resctrl detection

Class diagram for updated resctrl and Hygon CPU structures

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[Deepin-Kernel-SIG] [linux 6.6.y] [Upstream] update hygon qos to new version #1471

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Sequence diagram for Hygon CPU init calling common resctrl detection

Class diagram for updated resctrl and Hygon CPU structures

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