Dataflow Architecture

This repo aims to collect papers, docs, slides and codes about dataflow architecture. We are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo.

Dataflow architecture is a dataflow-based computer architecture that directly contrasts the traditional von Neumann architecture or control flow architecture. wiki

Table of Contents

Company

• Tenstorrent, Jim Keller
• Sambanova, Kunle
• SimpleMachine
• cerebras

Papers

2023

• [ICCAD] Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators

• [ICCAD] FLEX : Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow

• [arxiv] Revet: A Language and Compiler for Dataflow Threads, Kunle

• [OSDI 23] Welder: Scheduling Deep Learning Memory Access via Tile-graph, Shi link

• [OSDI] COCKTAILER: Analyzing and Optimizing Dynamic Control Flow in Deep Learning

2022

• [MICRO] RipTide: A Programmable, Energy-Minimal Dataflow Compiler and Architecture, Tony
• [ISCA] The Mozart reuse exposed dataflow processor for AI and beyond: industrial product, Tony
• [ISSCC] SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0

2021

• [arxiv] RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure, ICT
• 数据流计算研究进展与概述

2020

• [HPCA] A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms, Tony
• [FGCS] An efficient dataflow accelerator for scientific applications, ICT
• 从计算机体系结构发展历程看数据流计算思想

2019

• [Commun. ACM] Heterogeneous Von Neumann/dataflow microprocessors, Tony

• [ACM Computing] A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications, Tsinghua

• [MICRO] Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach

2018

2017

• [ISCA] Stream-dataflow acceleration, Tony
• [ISCA] Plasticine: A reconfigurable architecture for parallel patterns, Kunle
• [HPCA] FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

2016

• [JSSC] Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

2015

• [ISCA] Exploring the potential of heterogeneous von neumann/dataflow execution models, Tony
• [MICRO] A scalable architecture for ordered parallelism, MIT

2014

• [ISCA] HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs, Havard

• [Dataflow]DFGR: an Intermediate Graph Representation for Macro-Dataflow Programs

2013

• [Dataflow] The Flexible Preconditions Model for Macro-Dataflow Execution

Before

• [DSD'13] The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices
• [EXADAPT'11] Using a "codelet" program execution model for exascale machines: position paper
• [ISCA'04] TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
• [MICRO'03] WaveScalar
• [Computer'1997] aring it all to software: Raw machines
• [TC'1990] Executing a program on the MIT tagged-token dataflow architecture
• [IEEE‘1987] Synchronous data flow
• [ACM Computing] Dataflow machine architecture
• [Commun. ACM'1985] The Manchester prototype dataflow computer
• [ISCA'1975] A preliminary architecture for a basic data-flow processor