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arm64: dts: amlogic: radxa-zero: 270 clock phase, via amlogic,mmc-phase #526

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arm64: dts: amlogic: radxa-zero: 270 clock phase, via amlogic,mmc-phase #526

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281d0d8
arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase cl…
adeepn Nov 7, 2022
5b16d23
arm64: amlogic: dts: meson: update meson-axg device-tree for new core…
adeepn Nov 7, 2022
bcb1f01
arm64: dts: docs: Update mmc meson-gx documentation for new config op…
adeepn Nov 10, 2022
acc5121
arm64: dts: amlogic: radxa-zero: 270 clock phase, via amlogic,mmc-phase
LZhaoM Feb 5, 2026
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11 changes: 11 additions & 0 deletions Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,16 @@ properties:
power-domains:
maxItems: 1

amlogic,mmc-phases:
type: integer
description: |
3-element array of clock phases for core, tx, rx clock with values:
0: CLK_PHASE_0 - 0 phase
1: CLK_PHASE_90 - 90 phase
2: CLK_PHASE_180 - 180 phase
3: CLK_PHASE_270 - 270 phase
By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.

required:
- compatible
- reg
Expand All @@ -76,4 +86,5 @@ examples:
clock-names = "core", "clkin0", "clkin1";
pinctrl-0 = <&emm_pins>;
resets = <&reset_mmc>;
amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
};
3 changes: 3 additions & 0 deletions arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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Expand Up @@ -13,6 +13,7 @@
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
#include <dt-bindings/power/meson-axg-power.h>
#include <dt-bindings/mmc/meson-gx-mmc.h>

/ {
compatible = "amlogic,meson-axg";
Expand Down Expand Up @@ -1959,6 +1960,7 @@
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
resets = <&reset RESET_SD_EMMC_B>;
};

Expand All @@ -1972,6 +1974,7 @@
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
};

nfc: nand-controller@7800 {
Expand Down
3 changes: 3 additions & 0 deletions arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/mmc/meson-gx-mmc.h>

/ {
compatible = "radxa,zero", "amlogic,g12a";
Expand Down Expand Up @@ -477,6 +478,8 @@
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;

amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
};

&tdmif_b {
Expand Down
19 changes: 13 additions & 6 deletions drivers/mmc/host/meson-gx-mmc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/bitfield.h>
#include <linux/pinctrl/consumer.h>
#include <dt-bindings/mmc/meson-gx-mmc.h>

#define DRIVER_NAME "meson-gx-mmc"

Expand All @@ -36,8 +37,6 @@
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
#define CLK_TX_PHASE_MASK GENMASK(11, 10)
#define CLK_RX_PHASE_MASK GENMASK(13, 12)
#define CLK_PHASE_0 0
#define CLK_PHASE_180 2
#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
#define CLK_V2_ALWAYS_ON BIT(24)
Expand Down Expand Up @@ -426,13 +425,21 @@ static int meson_mmc_clk_init(struct meson_host *host)
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
const char *clk_parent[1];
u32 clk_reg;

u32 phase[3]; // <core_phase, tx_phase, rx_phase>

if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
"amlogic,mmc-phase", phase, 3) < 0)) {
dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
phase[0] = CLK_PHASE_180;
phase[1] = CLK_PHASE_0;
phase[2] = CLK_PHASE_0;
}
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = CLK_ALWAYS_ON(host);
clk_reg |= CLK_DIV_MASK;
clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
Expand Down
35 changes: 35 additions & 0 deletions include/dt-bindings/mmc/meson-gx-mmc.h
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@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2022 Vyacheslav Bocharov
* Author: Vyacheslav Bocharov <adeep@lexina.in>
*/

#ifndef _DT_BINDINGS_MESON_GX_MMC_H
#define _DT_BINDINGS_MESON_GX_MMC_H

/*
* Cfg_rx_phase: RX clock phase
* bits: 9:8 R/W
* default: 0
* Recommended value: 0
*
* Cfg_tx_phase: TX clock phase
* bits: 9:8 R/W
* default: 0
* Recommended value: 2
*
* Cfg_co_phase: Core clock phase
* bits: 9:8 R/W
* default: 0
* Recommended value: 2
*
* values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
*/

#define CLK_PHASE_0 0
#define CLK_PHASE_90 1
#define CLK_PHASE_180 2
#define CLK_PHASE_270 3


#endif